1. Field of the Invention
This invention relates generally to the testing of memory devices and, more particularly, to an automated method of burn-in and endurance testing of non-volatile memory.
2. Description of the Prior Art
Upon completion of the manufacturing process, testing is usually performed to detect manufacturing defects in an integrated circuit. Traditionally, testing is performed on a commercial test machine by either probing the semiconductor wafer itself (prior to packaging into a chip) or testing a completed part through its package pins. The type of test performed, whether on the wafer or on the completed chip, is dependent upon the type of integrated circuit. For example, a non-volatile memory circuit will undergo memory testing to ensure the proper operation of the non-volatile memory. As is well known in the art, non-volatile memory retains its stored data even after the power is removed from the circuit. Examples of non-volatile memory include electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EPROM.
A complex integrated circuit contains a mixture of logic and memory devices. Due to this mixture, the complex circuit requires the testing of all of the logical and the memory devices to ensure its proper operation. FIG. 1 illustrates a block diagram of an integrated circuit 100 having embedded non-volatile memory 104 and a processor 102. The circuit 100 also includes static random access memory (SRAM) 106. The processor 102, non-volatile memory 104 and the SRAM 106 are connected to each other by a bus 110. The bus 110 has sufficient address, data and control lines such that the processor 102 can communicate with the non-volatile memory 104 and the SRAM 106. As part of the manufacturing process of the completed part (i.e., the chip), connections to external devices are brought out to the package pins (e.g., the clock and reset lines illustrated in FIG. 1). The testing of the embedded non-volatile memory 104 now follows.
One conventional method of testing non-volatile memory 104 is to perform a burn-in test. A burn-in test is used to establish whether the non-volatile memory 104 will break down and become ineffective after being placed under a continuous high stress condition such as an elevated operating temperature.
Generally, a burn-in test is performed by connecting the integrated circuit 100 having the embedded non-volatile memory 104 to a test board and then placing the test board into a burn-in oven. Once in the oven, the circuit's 100 temperature is elevated and its non-volatile memory 104 is exercised by test equipment within the oven. During the burn-in test, the entire non-volatile memory 104 is exercised by continuous read operations (also referred to as "read cycles") for a period of time. The time period varies and is adjusted to meet the desired specifications of the integrated circuit 100. Upon completion of the burn-in test, the test board is removed from the burn-in oven. The non-volatile memory 104 is subsequently tested by another test unit or "test set" to determine if the stress of the burn-in test exposed any defects.
A second conventional method of testing non-volatile memory 104 is by endurance testing. As is well known in the art, non-volatile memories "wearout" (i.e., become ineffective after a limited number of programming and erase operations). The endurance test is used to establish whether the non-volatile memory 104 is capable of undergoing at least a predefined number of erase and programming operations. The predefined number of erase and programming operations varies and is adjusted to meet the desired specifications of the integrated circuit 100.
Generally, an endurance test is performed by connecting the integrated circuit 100 having the non-volatile memory 104 to a test board and then alternately performing erase and programming operations on the memory 104 for a predetermined number of endurance cycles (where an endurance cycle is the completion of one erase operation followed by one programming operation). Upon completion of the endurance test, the non-volatile memory 104 is subsequently tested by a test set to determine if there is premature wearout, or other defects, in the non-volatile memory 104.